Challenges in Manufacturing FinFET at 20nm node and beyond

Recently, there is strong interest in FinFET technology on bulk for lower cost and good compatibility with planar CMOS. Intel’s 22nm CMOS node is the 1 st commercially available bulk-FinFET technology and opens a new era of 3D CMOS for the low-power mobile electronics and continuously driving CMOS scaling and Moore’s law. The challenges in manufacturing FinFETs are reviewed. The Si surface of fins appears different than in bulk and result in excessive Si loss in wet cleans, oxidation, and dry etching. The shape of active fins leads to preferred low-doping in channel for minimizing variations of Vt . Then, multi-Vcc scheme is used for SOC instead of the multi-Vt scheme (based on multiple work-function of gate). In order to prevent dopant diffusion into the channel, the fins are preferably formed on SOI or bulk substrate with super-steep retrograde well (SSRW) doping. Finally, the contact and gate metals provide new knobs (in addition to the usual stressor S/D epi) for strain engineering for FinFETs toward higher performance at lower Vcc and power.